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Preliminary Information
This X84160/640/128 device has been acquired by IC MICROSYSTEMS from Xicor, Inc.
ICmic
TM
IC MICROSYSTEMS
16K/64K/128K
X84160/640/128
MPSTM EEPROM
Advanced MPSTM Micro Port Saver EEPROM with Block LockTM Protection
FEATURES
*Up to 15MHz data transfer rate *20ns Read Access Time *Direct Interface to Microprocessors and Microcontrollers --Eliminates I/O port requirements --No interface glue logic required --Eliminates need for parallel to serial converters *Low Power CMOS --1.8V-3.6V, 2.5V-5.5V and 5V 10% Versions --Standby Current Less than 1A --Active Current Less than 1mA *Byte or Page Write Capable --32-Byte Page Write Mode *New Programmable Block LockTM Protection --Software Write Protection --Programmable Hardware Write Protection *Block Lock (0, 1/4, 1/2, or all of the array) *Typical Nonvolatile Write Cycle Time: 3ms *High Reliability --100,000 Endurance Cycles --Guaranteed Data Retention: 100 Years *Small Package Options --8-Lead Mini-DIP Package --8, 14-Lead SOIC Packages --8, 20, 28-Lead TSSOP Packages --8-Lead XBGA Packages
bytewide memory control functions, takes a fraction of the board space and consumes much less power. Replacing serial memories, the Port Saver provides all the serial benefits, such as low cost, low power, low voltage, and small package size while releasing I/Os for more important uses. The Port Saver memory outputs data within 20ns of an active read signal. This is less than the read access time of most hosts and provides "no-wait-state" operation. This prevents bottlenecks on the bus. With rates to 15MHz, the Port Saver supplies data faster than required by most host read cycle specifications. This eliminates the need for software NOPs. The Port Saver memories communicate over one line of the data bus using a sequence of standard bus read and write operations. This "bit serial" interface allows the Port Saver to work well in 8-bit, 16 bit, 32-bit, and 64-bit systems. The X84160/640/128 provide additional data security features through Block Lock and programmable Hardware Write Protection. These allow some or all of the array to be write protected by software command or by hardware. System Configuration, Company ID, calibration information, or other critical data can be secured against unexpected or inadvertent program operations, leaving the remainder of the memory available for the system or user access A Write Protect (WP) pin prevents inadvertent writes to the memory. Xicor EEPROMs are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years.
DESCRIPTION
The Port Saver memories need no serial ports or special hardware and connect to the processor memory bus. Replacing bytewide data memory, the Port Saver uses
BLOCK DIAGRAM
System Connection
P C
A15 WP
Internal Block Diagram MPS
H.V. GENERATION TIMING & CONTROL
DSP ASIC RISC
Ports Saved
P0/CS P1/CLK P2/DI
A0 D7
CE I/O
COMMAND DECODE
D0 OE WE
OE WE
AND CONTROL
X DEC
EEPROM ARRAY 16K x 8
8K x 8 2K x 8
LOGIC
P3/DO
Y DECODE DATA REGISTER
(c) Xicor, Inc. 1998 Patents Pending
7067 1.1 6/10/98 T10/C0/D3
1
Characteristics subject to change without notice
X84160/640/128
PIN CONFIGURATIONS: Drawings are to the same scale, actual package sizes are shown in inches:
8-LEAD PDIP 8-LEAD SOIC CE I/O WP V SS 1 2 X84160 3 X84640 4 .230 in. 8 7 6 5 V CC NC OE WE .190 in. NC VCC CE I/O 8-LEAD TSSOP 1 2 3 4 8 7 6 5 OE WE WP VSS
PIN NAMES
.114 in.
X84160
I/O CE OE WE WP
Data Input/Output Chip Enable Input Write Enable Input Supply Voltage Ground Output Enable Input Write Protect Input
14-LEAD SOIC CE I/O NC NC NC WP V SS 1 2 3 4 5 6 7 .230 in. X84128 14 13 12 11 10 9 8 V CC NC NC NC NC OE WE .390 in.
NC NC CE I/O NC NC NC WP VSS NC
1 2 3 4 5 6 7 8 9 10
X84640
20 19 18 17 16 15 14 13 12 11
NC NC VCC NC NC NC NC OE WE NC
.250 in.
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NC NC NC NC VCC NC NC .394 in. NC NC OE WE NC NC NC
.252 in. 28-LEAD TSSOP NC NC CE CE CE I/O NC NC NC WP VSS NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
8-LEAD XBGA: Top View VCC 1 8 I/O .238 in. NC WE OE 2 7 CE 3 6 VSS 4 5 WP
P
2
X84128
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. 252 in.
.078 in.
PIN DESCRIPTIONS Chip Enable (CE)
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The Chip Enable input must be LOW to enable all read/ write operations. When CE is HIGH, the chip is deselected, the I/O pin is in the high impedance state, and unless a nonvolatile write operation is underway, the device is in the standby power mode. Output Enable (OE) The Output Enable input must be LOW to enable the output buffer and to read data from the device on the I/O line.
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Write Protect (WP) The Write Protect input controls the Hardware Write Protect feature. When WP is LOW and the nonvoltaile bit WPEN is "1", nonvolatile writes of the X84160/640/128 control register is disabled, but the part otherwise functions normally. When WP is held HIGH, all functions, including nonvolatile write operate normally. WP going LOW while CS is still LOW will interrupt a write to the X84160/640/128 control register. If the internal Write cycle has already been initiated, WP going LOW will have no effect on write. The WP pin function is blocked when the WPEN bit in the control register is "0". This allows the user to install the X84160/640/128 in a system with WP pin grounded and still be able to write to the control register. The WP pin functions will be enabled when the WPEN bit is set "1".
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Write Enable (WE) The Write Enable input must be LOW to write either data or command sequences to the device. Data In/Data Out (I/O) Data and command sequences are serially written to or serially read from the device through the I/O pin.
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VCC VSS NC No Connect
20-LEAD TSSOP
PACKAGE SELECTION GUIDE
84160
8-Lead PDIP 8-Lead SOIC 8-Lead TSSOP 8-Lead CSP/BGA 8-Lead PDIP 8-Lead SOIC 20-Lead TSSOP 8-Lead CSP/BGA 8-Lead PDIP 14-Lead SOIC 28-Lead TSSOP
84640
84128
t
.252 in.
X84160/640/128
DEVICE OPERATION The X84160/640/128 are serial EEPROMs designed to interface directly with most microprocessor buses. Standard CE, OE, and WE signals control the read and write operations, and a single l/O line is used to send and receive data and commands serially. Data Timing Data input on the l/O line is latched on the rising edge of either WE or CE, whichever occurs first. Data output on the l/O line is active whenever both OE and CE are LOW. Care should be taken to ensure that WE and OE are never both LOW while CE is LOW. Read Sequence A read sequence consists of sending a 16-bit address followed by the reading of data serially. The address is written by issuing 16 separate write cycles (WE and CE LOW, OE HIGH) to the part without a read cycle between the write cycles. The address is sent serially, most significant bit first, over the I/O line. Note that this sequence is fully static, with no special timing restrictions, and the processor is free to perform other tasks on the bus whenever the device CE pin is HIGH. Once the 16 address bits are sent, a byte of data can be read on the I/O line by issuing 8 separate read cycles (OE and CE LOW, WE HIGH). At this point, writing a `1' will terminate the read sequence and enter the low power standby state, otherwise the device will await further reads in the sequential read mode. Sequential Read The byte address is automatically incremented to the next higher address after each byte of data is read. The data stored in the memory at the next address can be read sequentially by continuing to issue read cycles. When the highest address in the array is reached, the address counter rolls over to address 0000h and reading may be continued indefinitely. Reset Sequence The reset sequence resets the device and sets an internal write enable latch. A reset sequence can be sent at any time by performing a read/write "0"/read operation (see Figs. 1 and 2). This breaks the multiple read or write cycle sequences that are normally used to read from or write to the part. The reset sequence can be used at any time to interrupt or end a sequential read or page load. As soon as the write "0" cycle is complete, the part is reset (unless a nonvolatile write cycle is in progress). The second read cycle in this sequence, and any further read cycles, will read a HIGH on the l/O pin until a valid read sequence (which includes the address) is issued. The reset sequence must be issued at the beginning of both read and write sequences to be sure the device initiates these operations properly.
Figure 1. Read Sequence
CE
O
bs
OE
WE
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I/O (IN)
"0"
A15 A14 A13 A12 A11 A10 A9 A8
e
P
3
A7 A6 A5 A4 A3 A2
I/O (OUT) RESET
WHEN ACCESSING: X84160 ARRAY: A15-A11=0 X84640 ARRAY: A15-A13=0 X84128 ARRAY: A15-A14=0
LOAD ADDRESS
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A1 A0
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D7 D6 D5 D4 D3 D2 D1 D0
READ DATA
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7008 FRM F04.1
X84160/640/128
Figure 2: Write Sequence
CE
OE
WE
I/O (IN)
"0"
A15 A14 A13 A12 A11 A10 A9 A8
A7 A6 A5 A4 A3 A2 A1 A0
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D7 D6 D5 D4 D3 D2 D1 D0
RESET
WHEN ACCESSING: X84160 ARRAY: A15-A11=0 X84640 ARRAY: A15-A13=0 X84128 ARRAY: A15-A14=0
LOAD ADDRESS
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I/O (OUT)
LOAD DATA
P
4
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Write Sequence A nonvolatile write sequence consists of sending a reset sequence, a 16-bit address, up to 32 bytes of data, and then a special "start nonvolatile write cycle" command sequence.
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page, where data loading can continue. For this reason, sending more than 256 consecutive data bits will result in overwriting previous data. A nonvolatile write cycle will not start if a partial or incomplete write sequence is issued. The internal write enable latch is reset when the nonvolatile write cycle is completed and after an invalid write to prevent inadvertent writes. Note that this sequence is fully static, with no special timing restrictions. The processor is free to perform other tasks on the bus whenever the chip enable pin (CE) is HIGH. Nonvolatile Write Status The status of a nonvolatile write cycle can be determined at any time by simply reading the state of the l/O pin on the device. This pin is read when OE and CE are LOW and WE is HIGH. During a nonvolatile write cycle the l/O pin is LOW. When the nonvolatile write cycle is complete, the l/O pin goes HIGH. A reset sequence can also be issued during a nonvolatile write cycle with the same result: I/O is LOW as long as a nonvolatile write cycle is in progress, and l/O is HIGH when the nonvolatile write cycle is done.
The nonvolatile write cycle is initiated by issuing a special read/write "1"/read sequence. The first read cycle ends the page load, then the write "1" followed by a read starts the nonvolatile write cycle. The device recognizes 32byte pages (e.g., beginning at addresses XXXXXX00000 for X84160). When sending data to the part, attempts to exceed the upper address of the page will result in the address counter "wrapping-around" to the first address on the
O
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The reset sequence is issued first (as described in the Reset Sequence section) to set an internal write enable latch. The address is written serially by issuing 16 separate write cycles (WE and CE LOW, OE HIGH) to the part without any read cycles between the writes. The address is sent serially, most significant bit first, on the l/O pin. Up to 32 bytes of data are written by issuing a multiple of 8 write cycles. Again, no read cycles are allowed between writes.
t
"1" "0" START NONVOLATILE WRITE
7008 FRM F05.1
X84160/640/128
CONTROL REGISTER The X84160/640/128 has one register that contains control bits for the devices. The control bits, WPEN, BP1, and BP0, are shown in Table 1. To read or change the contents of this register requires a one byte operation to address FFFFh. A read from FFFFh returns the one byte contents of the control register unused bits return 0. Continued reads return undefined data. A write to address FFFFh changes the value of the bits. Unused bits are written as "0". Writing more than one byte to the control register is a violation and the operation will be aborted. After sending one byte to the control register, a start nonvolatile write cycle will latch in the new state. Table 1 7 WPEN 6 0 5 0 4 0 3 BP1 2 BP0 1 0 0 0 The Write Protect (WP) pin and the nonvolatile Write Protect Enable (WPEN) bit in the Status Register control the programmable hardware write protect feature. Hardware write protection is enabled when WP pin is LOW, and the WPEN bit is "1". Hardware write protection is disabled when either the WP pin is HIGH or the WPEN bit is "0". When the chip is hardware write protected, nonvolatile write is disabled to the Control Register, including the Block Protect bits and the WPEN bit itself, as well as the block-protected sections in the memory array. Only the sections of the memory array that are not block-protected can be written.
Note: When the WP pin is tied to VSS and the WPEN bit is HIGH, the WPEN bit is write protected. It cannot be changed back to a "0", as long as the WP pin is held LOW.
WPEN 0 1 X
WP X LOW HIGH
Protected Blocks Protected Protected
Unprotected Blocks Writable Writable
Protected
Table 3. Block Lock Protection
bs
Control Register Bits BP1 0 0 1 1 BP0 0 1 0 1
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Writable
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WPEN: Write Protect Enable Bit The Write-Protect-Enable (WPEN) bit is an enable bit for the WP pin. Table 2
Status Register Writable
BP1, BP0: Block Protect Bits The Block Protect (BP0 and BP1) bits are nonvolatile and allow the user to select one of four levels of protection. The X84160/640/128 is divided into four segments. One, two, or all four of the segments may be protected. That is, the user may read the segments but will be unable to alter (write) data within the selected segments. The partitioning is controlled as illustrated in table 3 below.
Protected Writable
X84160 None 0600h-07FFh 0400h-07FFh 0000-07FFh
P
X84640 None
5
Array Address Protected X84128 None 3000h-3FFFh 2000h-3FFFh 0000h-3FFFh upper 1/4 upper 1/2 Full Array (Not including the control register.) Array
1800h-1FFFh 1000h-1FFFh 0000-1FFFh
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t
X84160/640/128
Low Power Operation The device enters an idle state, which draws minimal current when: --an illegal sequence is entered. The following are the more common illegal sequences: * Read/Write/Write--any time * Read/Write `1'--When writing the address or writing data. * Write `1'--when reading data * Read/Read/Write `1'--after data is written to device, but before entering the NV write sequence. --the device powers-up; --a nonvolatile write operation completes. While a sequential read is in progress, the device remains in an active state. This state draws more current than the idle state, but not as much as during a read itself. To go back to the lowest power condition, an invalid condition is created by writing a `1' after the last bit of a read operation. Write Protection The following circuitry has been included to prevent inadvertent nonvolatile writes: --The internal Write Enable latch is reset upon power-up. --A reset sequence must be issued to set the internal write enable latch before starting a write sequence. --A special "start nonvolatile write" command sequence is required to start a nonvolatile write cycle.
--The internal Write Enable latch is reset and remains reset as long as the WP pin is LOW, which blocks all nonvolatile write cycles. --The internal Write Enable latch resets on an invalid write operation. SYMBOL TABLE
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WAVEFORM 6
P
e
O
bs
ol et
du c
INPUTS Must be steady May change from LOW to HIGH May change from HIGH to LOW Don't Care: Changes Allowed N/A Will be steady
OUTPUTS
Will change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known Center Line is High Impedance
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--The internal Write Enable latch is reset automatically at the end of a nonvolatile write cycle.
X84160/640/128
ABSOLUTE MAXIMUM RATINGS* Temperature under Bias ...................... -65C to +135C Storage Temperature ........................... -65C to +150C Terminal Voltage with Respect to VSS .......................................-1V to +7V DC Output Current................................................... 5mA Lead Temperature (Soldering, 10 seconds)..........300C RECOMMENDED OPERATING CONDITIONS Temperature Commercial Industrial Min. 0C -40C Max. +70C +85C +125C *COMMENT Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Supply Voltage X84160/640/128
X84160/640/128 - 2.5 X84160/640/128 - 1.8
D.C. OPERATING CHARACTERISTICS (VCC = 5V 10%) (Over the recommended operating conditions, unless otherwise specified.) Symbol ICC1 Parameter VCC Supply Current (Read) Min.
P
Max. 1
2 1 10 10 VCC x 0.3 VCC + 0.5 0.4
7
Limits
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Units mA Test Conditions OE = VIL, WE = VIH, I/O = Open, CE clocking = VCC x 0.1/VCC x 0.9 @ 10 MHz
ICC During Nonvolatile Write Cycle All Inputs at CMOS Levels CE = VCC, Other Inputs = VCC or VSS VIN = VSS to VCC VOUT = VSS to VCC mA A A A V V V V IOL = 2.1mA IOH = -1mA
Military -55C Notes: Contact factory for Military availability
ISB1 ILI ILO VlL (1) VIH
(1)
VCC Standby Current
Input Leakage Current
Output Leakage Current Input LOW Voltage
Input HIGH Voltage
bs
VOL
Output LOW Voltage Output HIGH Voltage VCC - 0.8
VOH
Notes: (1) VIL Min. and VIH Max. are for reference only and are not tested.
O
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ICC2
VCC Supply Current (Write)
e
-0.5
VCC x 0.7
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t
Limits 4.5V to 5.5V 2.5V to 5.5V 1.8V to 3.6V
X84160/640/128
D.C. OPERATING CHARACTERISTICS (VCC = 2.5V to 5.5V) (Over the recommended operating conditions, unless otherwise specified.) Symbol Parameter Limits Min. Max. 300 Units Test Conditions OE = VIL, WE = VIH, I/O = Open, CE clocking = VCC x 0.1/VCC x 0.9 @ VCC = 2.5, 5 MHz ICC During Nonvolatile Write Cycle All Inputs at CMOS Levels CE = VCC, Other Inputs = VCC or VSS VIN = VSS to VCC VOUT = VSS to VCC
ICC1
VCC Supply Current (Read)
A
ICC2 ISB1 ILI ILO VlL(1) VIH(1) VOL VOH
VCC Supply Current (Write) VCC Standby Current Input Leakage Current Output Leakage Current Input LOW Voltage Input HIGH Voltage Output LOW Voltage Output HIGH Voltage VCC - 0.4 -0.5 VCC x 0.7
2 1 10 10 VCC x 0.3
mA A A A V
VCC + 0.5 0.4
P
Max. 200 1 1 10 10 VCC x 0.3 VCC + 0.5 0.4
8
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Symbol
Parameter
e
D.C. OPERATING CHARACTERISTICS (VCC = 1.8V to 3.6V) (Over the recommended operating conditions, unless otherwise specified.) Limits Min. Units Test Conditions OE = VIL, WE = VIH, I/O = Open, CE clocking = VCC x 0.1/VCC x 0.9 @ VCC = 1.8V, 4 MHz ICC During Nonvolatile Write Cycle All Inputs at CMOS Levels CE = VCC, Other Inputs = VCC or VSS VIN = VSS to VCC VOUT = VSS to VCC
ICC1
VCC Supply Current (Read)
ICC2 ISB1 ILI ILO
VCC Supply Current (Write) VCC Standby Current
bs
Input Leakage Current Output Leakage Current Input LOW Voltage Input HIGH Voltage Output LOW Voltage Output HIGH Voltage VCC - 0.2 -0.5 VCC x 0.7
VlL(1)
O
VIH(1) VOL VOH
Notes: (1) VIL Min. and VIH Max. are for reference only and are not tested.
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V V V A mA A A A V V V V
du c
IOL = 1mA, VCC = 3V IOH = -400A, VCC = 3V IOL = 0.5mA, VCC = 2V IOH = -250A, VCC = 2V
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X84160/640/128
CAPACITANCE Symbol CI/O(2) CIN(2) TA = +25C, f = 1MHz, VCC = 5V Parameter Input/Output Capacitance Input Capacitance Max. 8 6 Units pF pF Test Conditions VI/O = 0V VIN = 0V
POWER-UP TIMING Symbol tPUR(3) tPUW(3) Parameter Power-up to Read Operation Power-up to Write Operation
A.C. CONDITIONS OF TEST Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels
5ns
VCC x 0.5
EQUIVALENT A.C. LOAD CIRCUITS
5V 2.06K OUTPUT 3.03K
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e
P
3V 2.8K OUTPUT 30pF 5.6K 30pF 2V
9
VCC x 0.1 to VCC x 0.9
2.39K
OUTPUT
30pF
4.58K
O
bs
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Notes: (3) Time delays required from the time the VCC is stable until the specific operation can be initiated. Periodically sampled, but not 100% tested.
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Max. 2 5
Notes: (2) Periodically sampled, but not 100% tested.
t
Units ms ms
X84160/640/128
A.C. CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.) Read Cycle Limits - X84160/640/128 VCC = 4.5V - 5.5V VCC = 2.5V - 5.5V VCC = 1.8V - 3.6V Symbol
tRC tCE tOE tOEL tOEH tLOW tHIGH tLZ
(4)
Parameter
Read Cycle Time CE Access Time OE Access Time OE Pulse Width OE High Recovery Time CE LOW Time CE HIGH Time CE LOW to Output In Low Z CE HIGH to Output In High Z OE LOW to Output In Low Z OE HIGH to Output In High Z Output Hold from CE or OE HIGH WE HIGH Setup Time WE HIGH Hold Time
Min.
70
Max
Min.
125
Max.
Min.
250
20 20 20 50 20 50 0 0 0 0 0 25 15 35 90 35 90 0
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25 70 25 70 70 180 70 180 0 0 0 25 0 0 25 25 30 30 25
t OEH t OHZ HIGH Z t HZ
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0 0 0 0 25 25
tHIGH tWEH tOH
tHZ(4) tOLZ(4) tOHZ tOH tWES tWEH
(4)
P
15
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25
Notes: (4) Periodically sampled, but not 100% tested. tHZ and tOHZ are measured from the point where CE or OE goes HIGH (whichever occurs first) to the time when I/O is no longer being driven into a 5pF load.
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tRC tLOW
tCE
CE
bs
WE
tWES tOE
t OEL
OE
O
I/O
t OLZ t LZ
DATA
10
t
Max.
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
X84160/640/128
Write Cycle Limits - X84160/640/128 VCC = 4.5V - 5.5V VCC = 2.5V - 5.5V VCC = 1.8V - 3.6V Symbol tNVWC tWC
tWP tWPH tCS tCH tCP tCPH tOES tOEH tDS(6) tDH(6) tWPSU(7) tWPHD(7)
(5)
Parameter Nonvolatile Write Cycle Time Write Cycle Time
WE Pulse Width WE HIGH Recovery Time Write Setup Time Write Hold Time CE Pulse Width CE HIGH Recovery Time OE HIGH Setup Time OE HIGH Hold Time Data Setup Time Data Hold Time WP HIGH Setup WP HIGH Hold
Min.
Max.
5
Min.
Max.
5
Min.
Max.
5
Units ms ns
ns ns ns ns ns ns ns ns ns ns ns ns
70 20 50 0 0 20 50 25 25 12 5 100 100
125 35 90 0 0 35 90 25
250 50
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25 20 5
P
11
100 100
O
bs
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Notes: (5) tNVWC is the time from the falling edge of OE or CE (whichever occurs last) of the second read cycle in the "start nonvolatile write cycle" sequence until the self-timed, internal nonvolatile write cycle is completed. (6) Data is latched into the X84160/640/128 on the rising edge of CE or WE, whichever occurs first. (7) Periodically sampled, but not 100% tested.
e
du c
180 0 0 70 180 50 50 30 5 150 150
t
X84160/640/128
CE Controlled Write Cycle
tCPH tCP
CE
tOES tOEH
OE
tCS tCH tWP tWPH
WE
WP
tWPSU tDS
tWPHD tDH
I/O
DATA
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tCPH tWPH t WPHD t DH
WE Controlled Write Cycle
OE
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CE
tOES
t CS
WE
bs
WP
tWPSU tDS
I/O
e
tCP
tCH tOEH
tWP
P
DATA
tWC HIGH Z
tWC
O
12
du c
HIGH Z
t
X84160/640/128
8-LEAD XBGA TYPE
120030
50020
28020
I/O
VCC
CE
NC
391230
VSS 100030
WE
WP
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198230
43020
198230
P
OE 13
14020
O
bs
NOTE: ALL DIMENSIONS IN M ALL DIMENSIONS ARE TYPICAL VALUES
391230
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du c
14020
X84640Z: Bottom View
t
X84160/640/128
8-LEAD XBGA TYPE
120030
50020
I/O
VCC
CE
NC
P e
VSS WE
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150030
WP
OE
198230
bs
O
43030
198230
604630
14020
NOTE: ALL DIMENSIONS IN M ALL DIMENSIONS ARE TYPICAL VALUES
14
604630
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28020
du c
14020
X84128: Bottom View
t
X84160/640/128
8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
0.260 (6.60) 0.240 (6.10) PIN 1 INDEX PIN 1
0.300 (7.62) REF.
HALF SHOULDER WIDTH ON ALL END PINS OPTIONAL SEATING PLANE 0.150 (3.81) 0.125 (3.18)
P
0.325 (8.25) 0.300 (7.62)
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0.110 (2.79) 0.090 (2.29)
.073 (1.84) MAX.
bs
TYP .0.010 (0.25)
O
NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
15
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0.020 (0.51) 0.016 (0.41)
0.060 (1.52) 0.020 (0.51)
0.025 (0.64) 0.015 (0.38) 0.065 (1.65) 0.045 (1.14)
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0.145 (3.68) 0.128 (3.25) 0 15
t
0.430 (10.92) 0.360 (9.14)
X84160/640/128
8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80) 0.158 (4.00) PIN 1 INDEX
PIN 1
0.188 (4.78) 0.197 (5.00)
(4X) 7
P e
0.053 (1.35) 0.069 (1.75) 0.004 (0.19) 0.010 (0.25) 0.050" TYPICAL 0.050" TYPICAL 0.250" 0.0075 (0.19) 0.010 (0.25) FOOTPRINT 0.030" TYPICAL 8 PLACES
0 - 8
bs
O
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0.050 (1.27)
0.010 (0.25) 0.020 (0.50) X 45
0.016 (0.410) 0.037 (0.937)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
16
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0.014 (0.35) 0.019 (0.49)
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0.228 (5.80) 0.244 (6.20)
t
X84160/640/128
PACKAGING INFORMATION 14-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80) 0.158 (4.00) PIN 1 INDEX
0.228 (5.80) 0.244 (6.20)
0.014 (0.35) 0.020 (0.51) 0.336 (8.55) 0.345 (8.75)
(4X) 7
e
ol et
0.050 (1.27)
P
0.053 (1.35) 0.069 (1.75) 0.004 (0.10) 0.010 (0.25)
0.010 (0.25) X 45 0.020 (0.50)
bs
ro
0.050" T ypical 0.050" Typical
0.0075 (0.19) 0.010 (0.25)
PIN 1
0 - 8
0.250"
O
0.016 (0.410) 0.037 (0.937)
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
17
du c
0.030"Typical 14 Places
t
X84160/640/128
PACKAGING INFORMATION 8-LEAD PLASTIC, TSSOP PACKAGE TYPE V ,
.025 (.65) BSC
.169 (4.3) .252 (6.4) BSC .177 (4.5)
.0075 (.19) .0118 (.30)
ol et
e
0 - 8
.019 (.50) .029 (.75)
Detail A (20X)
bs
P
.002 (.05) .006 (.15)
.114 (2.9) .122 (3.1)
.047 (1.20)
O
See Detail "A"
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
18
ro
.010 (.25) Gage Plane Seating Plane .031 (.80) .041 (1.05)
du c
t
X84160/640/128
PACKAGING INFORMATION
20-LEAD PLASTIC, TSSOP P ACKAGE TYPE V
.025 (.65) BSC
.169 (4.3) .252 (6.4) BSC .177 (4.5)
.0075 (.19) .0118 (.30)
e
ol et
P
.019 (.50) .029 (.75) Detail A (20X)
.252 (6.4) .300 (6.6)
.002 (.05) .006 (.15)
0 - 8
bs
O
See Detail "A"
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
19
ro
.047 (1.20) .010 (.25) Gage Plane Seating Plane .031 (.80) .041 (1.05)
du c
t
X84160/640/128
PACKAGING INFORMATION
28-LEAD PLASTIC, TSSOP P ACKAGE TYPE V
.025 (.65) BSC
.169 (4.3) .252 (6.4) BSC .177 (4.5)
.0075 (.19) .0118 (.30)
e
ol et
P
.019 (.50) .029 (.75) Detail A (20X)
.394 (10.0)
.002 (.05) .006 (.15)
0 - 8
bs
O
See Detail "A"
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
20
ro
.047 (1.20) .010 (.25) Gage Plane Seating Plane .031 (.80) .041 (1.05)
du c
t
X84160/640/128
ORDERING INFORMATION X84160/640/128 P Device T G -V
VCC Range Blank = 4.5V to 5.5V, 10 MHz 2.5 = 2.5V to 5.5V, 5 MHz 1.8 = 1.8V to 3.6V, 4 MHz
G = RoHS Compliant Lead Free package Blank = Standard package. Non lead free
Temperature Range Blank = Commercial = 0C to +70C
E = Extended = -20C to +85C I = Industrial = -40C to +85C Military = -55 to +125 (contact factory) C C Packages:
X84160 P = 8-Lead PDIP S8 = 8-Lead SOIC
*PART MARK CONVENTION 8-Lead TSSOP
EYWW 8160XXG
V8 = 8-Lead TSSOP 8-Lead SOIC/PDIP Blank = 8-Lead SOIC P = 8-Lead PDIP G = RoHS compliant lead free AG = 1.8 to 3.6V, 0 to +70 C AH = 1.8 to 3.6V, -40 to +85C F = 2.5 to 5.5V, 0 to +70 C G = 2.5 to 5.5V, -40 to +85 C
X84160G XXX
Blank = 4.5 to 5.5V, 0 to +70 C I = 4.5 to 5.5V, -40 to +85 C
G = RoHS compliant lead free
X84640 P = 8-Lead PDIP S8 = 8-Lead SOIC
V20 = 20-Lead TSSOP Z = 8-Lead XBGA
AG = 1.8 to 3.6V, 0 to +70C
AH = 1.8 to 3.6V, -40 to +85 C F = 2.5 to 5.5V, 0 to +70 C
G = 2.5 to 5.5V, -40 to +85 C Blank = 4.5 to 5.5V, 0 to +70 C
I = 4.5 to 5.5V, -40 to +85C
8-Lead XBGA PACKAGE Complete Part Number
X84128 P = 8-Lead PDIP S14 = 14-Lead SOIC V28 = 28-Lead TSSOP
Z = 8-Lead XBGA
Top Mark XAP XAR XAN XAO
X84640ZE-2.5 X84640ZI-2.5 X84128ZE-2.5 X84128 ZI-2.5
*All parts and package types not included will receive standard marking.
21
X84160/640/128
LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied.
U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and additional patents pending.
LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
22

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